Clock divider for analysis of all clock edges
US6441656B1 · kind B1 · utility
3Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.