MCM—MLC technology
US6442041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Dec 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09681
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.