Differential signal path for high speed data transmission in flash memory
US6442069B1 · kind B1 · utility
4Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.