Processor architecture for virtualizing selective external bus transactions
US6442635B1 · kind B1 · utility
7Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1998 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Nov 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.