Flag generation scheme for FIFOs
US6442657B1 · kind B1 · utility
4Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more memory address signals. The flag/array address circuit may be configured to present one or more flag address signals in response to (i) one or more enable signals and (ii) a control signal. The flag logic circuit may be configured to present one or more logic flags in response to the one or more flag address signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.