Selectively powering X Y organized memory banks
US6442667B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits. A valid and equal unit indicates whether data received from the third multiplexer includes a cache valid tag indicating a valid address and a cache address matching the received address. This indicates a cache hit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.