Method and system for bypassing a fill buffer located along a first instruction path
US6442674B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.