Method and apparatus for testing circuits with multiple clocks
US6442722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, the circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of the core logic and/or an output connected to an input to the core logic, and configurable in scan mode in which the memory elements are connected to define one or more scan chains in each domain and in normal mode in which the memory elements are connected to the core logic in normal operational mode, the method comprising configuring the memory elements in scan mode; concurrently clocking a test stimulus into each scan chain of each clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to the main test clock signal, clocking the test stimulus at a shift clock rate derived from the main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to the main test clock signal, clocking all but a predetermined number of bits of the test stimulus at a first domain shift clock rate derived from t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.