Placement method for integrated circuit design using topo-clustering

US6442743B1 · kind B1 · utility

Assignee

• Monterey Design Systems, Inc. · US

Inventors

• Majid Sarrafzadeh · Villa Park, US
• Lawrence Pileggi · Pittsburgh, US
• Sharad Malik · Princeton, US
• Feroze P. Taraporevala · Los Altos, US
• Abhijeet Chakraborty · Sunnyvale, US
• Gary K. Yeap · Fremont, US
• Salil Ravindra Raje · Saratoga, US
• Lilly Shieh · Union City, US
• Douglas B. Boyle · Palo Alto, US
• Dennis Yamamoto · Los Altos, US

Key dates

• Filing date: Jun 12, 1998
• Grant date: Aug 27, 2002
• Expiry date: Jun 12, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/392
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.