Dual metal gate transistors for CMOS process
US6444512B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/891
Abstract
A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.