Method of operation of punch-through field effect transistor

US6444527B1 · kind B1 · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Brian H. Floyd · Sunnyvale, US
• Fwu-Iuan Hshieh · Saratoga, US
• Mike F. Chang · Cupertino, US

Key dates

• Filing date: Jan 11, 2000
• Grant date: Sep 3, 2002
• Expiry date: Jan 11, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.