Selective oxide deposition in the bottom of a trench
US6444528B1 · kind B1 · utility
49Cited by
12References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Aug 16, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.