Process for making fine pitch connections between devices and structure made by the process
US6444560B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jan 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. A stud is provided on the front surface of the chip, and a layer with interconnection wiring is formed on a transparent plate. The wiring layer includes a conducting pad on a surface thereof opposite the plate. A second layer is formed on top of the wiring layer, with a via formed therein to expose the conducting pad. The stud and via are then aligned and connected; the front surface of the chip thus contacts the second layer and the stud makes electrical contact with the conducting pad. A chip support is then attached to the device. An interface between the wiring layer and the plate is exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.