Roy Yu
42Patents
19h-index
52Co-inventors
84Inventor score
Filing activity: Dec 7, 1995 → Jul 19, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6599778B2 | Chip and wafer integration process using vertical connections | Electricity | 388 | Expired |
| US7354798B2 | Three-dimensional device fabrication method | Emerging Cross-Sectional Technologies | 231 | Expired |
| US6036809A | Process for releasing a thin-film structure from a substrate | Emerging Cross-Sectional Technologies | 67 | Expired |
| US6600224B1 | Thin film attachment to laminate using a dendritic interconnection | Electricity | 60 | Expired |
| US6864165B1 | Method of fabricating integrated electronic chip with an interconnect device | Electricity | 47 | Expired |
| US6444560B1 | Process for making fine pitch connections between devices and structure made by the process | Electricity | 38 | Expired |
| US6183588A | Process for transferring a thin-film structure to a substrate | Emerging Cross-Sectional Technologies | 31 | Expired |
| US7071031B2 | Three-dimensional integrated CMOS-MEMS device and process for making the same | Electricity | 31 | Expired |
| US6640021B2 | Fabrication of a hybrid integrated circuit device including an optoelectronic chip | Physics | 31 | Expired |
| US6281452A | Multi-level thin-film electronic packaging structure and related method | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6835589B2 | Three-dimensional integrated CMOS-MEMS device and process for making the same | Electricity | 28 | Expired |
| US6090633A | Multiple-plane pair thin-film structure and process of manufacture | Electricity | 26 | Expired |
| US5735452A | Ball grid array by partitioned lamination process | Electricity | 25 | Expired |
| US7344959B1 | Metal filled through via structure for providing vertical wafer-to-wafer interconnection | Electricity | 23 | Active |
| US8247895B2 | 4D device process and structure | Electricity | 21 | Active |
| US6998327B2 | Thin film transfer join process and multilevel thin film module | Electricity | 20 | Expired |
| US6856025B2 | Chip and wafer integration process using vertical connections | Electricity | 20 | Expired |
| US6099935A | Apparatus for providing solder interconnections to semiconductor and electronic packaging devices | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6737297B2 | Process for making fine pitch connections between devices and structure made by the process | Electricity | 20 | Expired |
| US7049697B2 | Process for making fine pitch connections between devices and structure made by the process | Electricity | 16 | Expired |
| US7564118B2 | Chip and wafer integration process using vertical connections | Electricity | 16 | Active |
| US6143117A | Process for transferring a thin-film structure to a temporary carrier | Emerging Cross-Sectional Technologies | 14 | Expired |
| US7388277B2 | Chip and wafer integration process using vertical connections | Electricity | 14 | Expired |
| US7566632B1 | Lock and key structure for three-dimensional chip connection and process thereof | Electricity | 13 | Active |
| US6678949B2 | Process for forming a multi-level thin-film electronic packaging structure | Emerging Cross-Sectional Technologies | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.