Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6444921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed. A first substrate and a sacrificial substrate are encapsulated in an encapsulant material to form a composite substrate, with a second substrate being formed from the cured encapsulate material. Alternatively, the second substrate may be provided by a separate substrate that is encapsulated along with the first substrate and the sacrificial s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.