Floating back gate electrically erasable programmable read-only memory(EEPROM)
US6445032B1 · kind B1 · utility
11Cited by
11References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.