Cell based array comprising logic, transfer and drive cells
US6445049B1 · kind B1 · utility
119Cited by
29References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A highly flexible, heterogeneous architecture for portable, high density, high performance standard cell and gate array applications is disclosed. The architecture is based on the three basic cells and their derivatives, particularly a transmission gate cell, a logic cell, and a drive cell. For gate array implementations, the cells are arranged in a pre-determined regular array format. For standard cell implementations, the arrangement of the cells may be optimized to suit each target logic gate. Optimized transistor sizing is achievable through leaf cells, software sizing, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.