Power lateral diffused MOS transistor
US6445052B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
The present invention provides a power lateral diffused metal-oxide semiconductor (power LD MOS) transistor positioned in an active area of a substrate on a semiconductor wafer. The power LD MOS transistor has a source/drain, a first metal layer and a hexagonal-shaped gate. The first metal layer is positioned on a second dielectric layer, covering the first dielectric layer, the gate, and the surface of the substrate, and is electrically connected with the drain via a first plug. A hexagonal-shaped gate positioned on the substrate surrounds the drain, with a first end of the gate positioned on the first dielectric layer and a second end connecting with the source. A second metal layer positioned on the second dielectric layer electrically connects with the drain via a second plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.