Semiconductor chip package
US6445077B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package includes a semiconductor chip and a substrate on which the semiconductor chip attaches. The semiconductor chip includes center and edge bonding pads. The substrate includes a first window that exposes the center bonding pads, a second window that exposes the edge bonding pads, connection pads around the first and second windows, external terminal pads, and a wiring pattern. The semiconductor chip package further includes bonding wires, an encapsulation body, and external terminals. The bonding wires connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate. A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads to corresponding connection pads; encapsulating side surfaces of the semiconductor chip, a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.