Column redundancy architecture system for an embedded DRAM
US6445626B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Apr 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.