Method and circuit configuration for processing digital signals
US6445753B1 · kind B1 · utility
0Cited by
6References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Aug 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a circuit configuration deactivate an input of a receiving circuit when a first edge occurs, during processing of a digital input signal. When a falling edge occurs, the input is only reactivated after a delay. An influence of signal interference and incorrect interpretations of the signal can thereby be reduced. The method and circuit configuration are employed in particular with clock signals in which only one edge is used for signal evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.