Computing system with volatile lock architecture for individual block locking on flash memory
US6446179B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Dec 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for protecting memory blocks in a block-based flash erasable programmable read only memory device are disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register is coupled to each of the lockable blocks in the memory array. A logic state is coupled to one input of the volatile lock register, and a block set/reset line is coupled to a second input of the volatile lock register. A block latch control line is coupled to one input of the logic gate, and a group latch control line is coupled to a second input of the logic gate. The method includes reading a first command of a multi-cycle command specifying a lock configuration of one or more memory blocks and reading a second command specifying the number of memory blocks to be lock configured. The method and apparatus allow a user to dynamically select which blocks of a flash array to lock or unlock and minimize the possibility of data corruption during block lock and unlock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.