Hybrid capacitor and method of fabrication therefor
US6446317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.