Method for fabricating a dual-chip package and package formed
US6448110B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a back-to-back dual-chip package and package formed are disclosed. In the method, a first IC chip is bonded in its inactive surface to an inactive surface of a second IC chip, while solder balls planted on the active surfaces of both chips. One of the chips is connected to lead fingers of a lead frame by the solder balls. The dual-chip assembly together with the lead fingers are then encapsulated in an insulating material for protecting the chips while exposing substantially the solder balls on the IC chip that was not connected to the lead fingers. The encapsulated assembly can then be connected to an outside circuit, such as a printed circuit board, by forming the exposed finger leads for soldering and by fusing the solder balls to the outside circuit. The present invention novel method and device formed advantageously utilize existing chip design for achieving a high density device at a low cost. For instance, by doubling up two memory chips and doubling its memory capacity, existing memory chip design and existing fabrication equipment can be utilized to avoid the high costs of a new high capacity chip design and a new fabrication equipment. The present inv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.