Totally self-aligned transistor with tungsten gate
US6448120B1 · kind B1 · utility
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13References
6Claims
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Key dates
| Filing date | Apr 17, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Apr 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.