Dual damascene processing for semiconductor chip interconnects
US6448176B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Oct 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/945
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.