Method for making a semiconductor device that has a dual damascene interconnect
US6448185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of forming a semiconductor device is described. In that method, a dielectric layer that comprises a carbon doped oxide is formed on a substrate. After a first etched region is formed in the dielectric layer, that region is filled with a sacrificial light absorbing material. A layer of photoresist is then deposited and patterned, followed by forming a second etched region by removing part of the sacrificial light absorbing material and a second part of the dielectric layer. Remaining portions of the photoresist are then removed by exposing the resulting device to a plasma generated from a forming gas. The device is then exposed to a solution for removing the remaining portions of the sacrificial light absorbing material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.