Multiple threshold voltage FET using multiple work-function gate materials

US6448590B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• Arne Ballantine · Palo Alto, US
• Ramachandra Divakaruni · Ossining, US
• Jeffrey B. Johnson · Hague, US
• Erin C. Jones · Yorktown Heights, US
• Hon-Sum Philip Wong · Chappaqua, US

Key dates

• Filing date: Oct 24, 2000
• Grant date: Sep 10, 2002
• Expiry date: Oct 24, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.