DRAM having a stacked capacitor and a method for fabricating the same
US6448597B1 · kind B1 · utility
5Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A DRAM includes a MOSFET and a stacked capacitor in each memory cell. The stacked capacitor includes a bottom electrode substantially of a cylindrical shape, a top electrode received in the cylindrical-shape bottom electrode, and a capacitor dielectric film for insulation therebetween. The cylindrical shape of the bottom electrode allows a larger deviation for alignment between the capacitor and the capacitor contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.