Chip decoupling capacitor
US6448628B2 · kind B2 · utility
8Cited by
31References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0231
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.