Voltage regulator for non-volatile memory with large power supply rejection ration and minimal current drain
US6448750B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A regulator circuit to deliver a regulated boosted voltage VPP from a charge pump to electrodes of the cells of a non-volatile memory (NVM) array, such as an EPROM, integrated circuit device. The regulator includes a differential amplifier operating from a VDD voltage lower than VPP that drives a gain stage whose output is to a current mirror operating from the boosted VPP voltage. The current mirror output is taken across a voltage divider as the regulated output of the circuit. The differential amplifier has one input at a fixed voltage and the other being a feedback voltage from the voltage divider to control the gain of the differential amplifier and thereby regulate the output of the gain stage and current mirror in response to a variable load current of the integrated circuit device. The circuit is capable of providing current at the boosted VPP voltage for programming the cells of the NVM while minimizing power consumption from the VDD supply of the charge pump and having a high PSRR (power supply rejection ratio) as compared to prior art circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.