Saifun Semiconductors Ltd.
124Patents
26Active
124Granted
45Portfolio score
Filing activity: Jul 23, 1996 → Apr 14, 2008 · 26 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6011725A | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | Electricity | 1,212 | Expired |
| US5768192A | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping | Physics | 1,055 | Expired |
| US6992932B2 | Method circuit and system for read error detection in a non-volatile memory array | Physics | 317 | Expired |
| US5966603A | NROM fabrication method with a periphery portion | Electricity | 291 | Expired |
| US6297096A | NROM fabrication method | Emerging Cross-Sectional Technologies | 199 | Expired |
| US6552387B1 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | Physics | 194 | Expired |
| US6030871A | Process for producing two bit ROM cell utilizing angled implant | Electricity | 187 | Expired |
| US6215148A | NROM cell with improved programming, erasing and cycling | Electricity | 162 | Expired |
| US6292394A | Method for programming of a semiconductor memory cell | Physics | 154 | Expired |
| US6201282A | Two bit ROM cell and process for producing same | Electricity | 149 | Expired |
| US6134156A | Method for initiating a retrieval procedure in virtual ground arrays | Physics | 148 | Expired |
| US6348711B1 | NROM cell with self-aligned programming and erasure areas | Electricity | 143 | Expired |
| US6429063B1 | NROM cell with generally decoupled primary and secondary injection | Electricity | 135 | Expired |
| US6477084B2 | NROM cell with improved programming, erasing and cycling | Electricity | 130 | Expired |
| US6490204B2 | Programming and erasing methods for a reference cell of an NROM array | Physics | 113 | Expired |
| US6396741B1 | Programming of nonvolatile memory cells | Physics | 110 | Expired |
| US6643181B2 | Method for erasing a memory cell | Physics | 107 | Expired |
| US6975536B2 | Mass storage array and methods for operation thereof | Physics | 102 | Expired |
| US5963465A | Symmetric segmented memory array architecture | Physics | 100 | Expired |
| US6566699B2 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | Physics | 90 | Expired |
| US6128226A | Method and apparatus for operating with a close to ground signal | Physics | 90 | Expired |
| US6768165B1 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | Electricity | 77 | Expired |
| US6928001B2 | Programming and erasing methods for a non-volatile memory cell | Physics | 64 | Expired |
| US6535434B2 | Architecture and scheme for a non-strobed read sequence | Physics | 63 | Expired |
| US6285574A | Symmetric segmented memory array architecture | Physics | 60 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.