Method and apparatus for programming flash memory device
US6449187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method is for programming a memory cell in an array of cells having a plurality of bit lines, each with bit-line coupled cells, and a plurality of word lines, each with word-line coupled cells. A word line-bit line combination identifies a target cell. Each cell has a drain, source, gate and floating gate arrayed upon a base common to the cells, all of which cooperate to establish a floating gate-to-source field in each cell. The method includes the steps of: (a) applying a select signal to a word line and a bit line coupled with the target cell; (b) providing an adjusted signal to the bit-line coupled cells to decrease strength of the floating gate-to-drain field for the bit-coupled cells; (c) programming the target cell; and (d) maintaining the adjusted signal at least until the programming is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.