Method and apparatus for improving caching within a processor system
US6449693B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor system is provided that comprises a plurality of L0 caches, a processor having a plurality of execution units, and an L1 cache for caching any data and instructions used by the processor. A portion of the execution units provided are configured so that each execution unit within the portion accesses one of the L0 caches. Each of the L0 caches is accessible by only one of the portion of the execution units, and each L0 cache caches a subset of any data used by the processor which is not cacheable by any of the other L0 caches. The processor system preferably comprises an instruction dispatcher that dispatches instructions executable by the processor and that selectively designates data as cacheable by only one of the L0 caches, preferably at dispatch time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.