Inventor · Williston, VT, US

Paul Gutwin

23Patents
5h-index
28Co-inventors
69Inventor score

Filing activity: Aug 30, 1991 → Dec 5, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6532520B1 Method and apparatus for allocating data and instructions within a shared cache Physics 34 Expired
US5239481A Method for measuring pulse distortion Physics 18 Expired
US5796621A Circuit delay abstraction tool Physics 12 Expired
US6178467A Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode Physics 9 Expired
US6829755B2 Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis Physics 7 Expired
US6449693B1 Method and apparatus for improving caching within a processor system Physics 5 Expired
US6588000B2 Method of partitioning large transistor design to facilitate transistor level timing Physics 3 Expired
US11532708B2 Stacked three-dimensional field-effect transistors Electricity 1 Active
US11923364B2 Double cross-couple for two-row flip-flop using CFET Electricity 1 Active
US12224281B2 Interdigitated device stack Electricity 0 Active
US11830852B2 Multi-tier backside power delivery network for dense gate-on-gate 3D logic Electricity 0 Active
US12218135B2 Wiring in diffusion breaks in an integrated circuit Electricity 0 Active
US12176293B2 Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration Electricity 0 Active
US11961802B2 Power-tap pass-through to connect a buried power rail to front-side power distribution network Electricity 0 Active
US11764113B2 Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds Electricity 0 Active
US12336274B2 Self-aligned method for vertical recess for 3D device integration Electricity 0 Active
US12051638B2 Integrated high efficiency transistor cooling Emerging Cross-Sectional Technologies 0 Active
US12002862B2 Inter-level handshake for dense 3D logic integration Performing Operations; Transporting 0 Active
US12414367B2 Tapered device for lateral gate all around devices Electricity 0 Active
US6671218B2 System and method for hiding refresh cycles in a dynamic type content addressable memory Physics 0 Expired
US11764266B2 Three-dimensional semiconductor device Electricity 0 Active
US11581242B2 Integrated high efficiency gate on gate cooling Electricity 0 Active
US11723187B2 Three-dimensional memory cell structure Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.