Memory bandwidth utilization through multiple priority request policy for isochronous data streams
US6449702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a system logic device for improving memory bandwidth utilization in a computer system with an isochronous data stream includes a FIFO for the isochronous data stream. The FIFO includes two watermarks. When the data level of the FIFO falls below a first watermark level, a low priority request is issued to a memory controller. If the data level of the FIFO falls below a second watermark level, a high priority memory request is issued to the memory controller. The low priority memory request is assigned the lowest priority level by the memory controller. The high priority request is assigned the highest priority level by the memory controller. The low priority request allows the isochronous data stream to retrieve small amounts of data from memory without negatively impacting overall system performance while the high priority request allows the isochronous data stream to retrieve larger amounts of data from memory within a fixed time in order to ensure that the FIFO never completely drains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.