Aditya Sreenivas
38Patents
15h-index
42Co-inventors
77Inventor score
Filing activity: Sep 5, 1995 → Dec 18, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6628294B1 | Prefetching of virtual-to-physical address translation for display data | Physics | 152 | Expired |
| US7103730B2 | Method, system, and apparatus for reducing power consumption of a memory | Emerging Cross-Sectional Technologies | 100 | Expired |
| US6496193B1 | Method and apparatus for fast loading of texture data into a tiled memory | Physics | 95 | Expired |
| US6078339A | Mutual exclusion of drawing engine execution on a graphics device | Physics | 45 | Expired |
| US6885374B2 | Apparatus, method and system with a graphics-rendering engine having a time allocator | Physics | 42 | Expired |
| US5761444A | Method and apparatus for dynamically deferring transactions | Physics | 40 | Expired |
| US6141023A | Efficient display flip | Physics | 39 | Expired |
| US6362826B1 | Method and apparatus for implementing dynamic display memory | Physics | 28 | Expired |
| US7051172B2 | Memory arbiter with intelligent page gathering logic | Physics | 24 | Expired |
| US6867779B1 | Image rendering | Physics | 24 | Expired |
| US7321369B2 | Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device | Physics | 23 | Expired |
| US6560657B1 | System and method for controlling peripheral devices | Physics | 21 | Expired |
| US6026451A | System for controlling a dispatch of requested data packets by generating size signals for buffer space availability and preventing a dispatch prior to a data request granted signal asserted | Physics | 20 | Expired |
| US6330646A | Arbitration mechanism for a computer system having a unified memory architecture | Physics | 18 | Expired |
| US6633299B1 | Method and apparatus for implementing smart allocation policies for a small frame buffer cache serving 3D and 2D streams | Physics | 17 | Expired |
| US6724389B1 | Multiplexing digital video out on an accelerated graphics port interface | Physics | 15 | Expired |
| US6792516B2 | Memory arbiter with intelligent page gathering logic | Physics | 13 | Expired |
| US6538650B1 | Efficient TLB entry management for the render operands residing in the tiled memory | Physics | 12 | Expired |
| US6650332B2 | Method and apparatus for implementing dynamic display memory | Physics | 10 | Expired |
| US6199149A | Overlay counter for accelerated graphics port | Physics | 10 | Expired |
| US6999091B2 | Dual memory channel interleaving for graphics and video | Physics | 9 | Expired |
| US7035984B2 | Memory arbiter with grace and ceiling periods and intelligent page gathering logic | Physics | 8 | Expired |
| US6954208B2 | Depth write disable for rendering | Physics | 8 | Expired |
| US6067090A | Data skew management of multiple 3-D graphic operand requests | Physics | 7 | Expired |
| US5696768A | Method and apparatus for data storage array tracking | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.