High-speed data transfer synchronizing system and method
US6449727B1 · kind B1 · utility
143Cited by
2References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | May 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One memory controller and a plurality of memory modules are connected to a data bus line, clock bus line, and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals output from the memory controller. This internal clock signal generating circuit has a function of adjusting the timing of a generated internal clock signal on the basis of a control signal in accordance with the position on the bus lines of a memory module having this internal clock signal generating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.