Method of forming a semiconductor device barrier layer

US6451181B1 · kind B1 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Dean J. Denning · Alamo, US
• Sam S. Garcia · Austin, US
• Bradley P. Smith · Youngstown, US
• Daniel J. Loop · Austin, US
• Gregory N. Hamilton · Pflugerville, US
• Md. Rabiul Islam · Austin, US
• Brian G. Anthony · Austin, US

Key dates

• Filing date: Mar 2, 1999
• Grant date: Sep 17, 2002
• Expiry date: Mar 2, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76871
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.