Method for forming a lower electrode by using an electroplating method
US6451666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. Then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. The dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.