Method of forming insulated metal interconnections in integrated circuits
US6451669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.