Minimized contamination of semiconductor wafers within an implantation system
US6452198B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/3171
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Contamination of semiconductor wafers are minimized during implantation processes within an implantation system. An implantation chamber of the implantation system and components within the implantation chamber are coated with additional material to minimize contaminants within the implantation chamber. For example, surfaces of the implantation chamber and/or the components of the implantation chamber are coated by performing an implantation process with a coating dopant before a semiconductor wafer is placed within the implantation chamber. In this manner, contaminants on the surfaces of the implantation chamber and/or the components within the implantation chamber are substantially coated and encapsulated with the coating dopant to prevent contact of the contaminant with the semiconductor wafer placed within the implantation chamber. Alternatively, shields are placed on surfaces of the implantation chamber and/or on surfaces of the components of the implantation chamber during an implantation process for a first semiconductor wafer having a contaminant source. Such shields are amenable for absorbing the contaminant and are removed after this implantation process and before a seco…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.