Insulated gate bipolar transistor and method of fabricating the same
US6452219B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1997 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Aug 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/913
Abstract
An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.