Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
US6452411B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Mar 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31905
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.