Method and apparatus for scanning and clocking chips with a high-speed free running clock in a manufacturing test environment
US6452435B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.