Packaging architecture for 32 processor server
US6452789B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.