Interleaved memory device for sequential access synchronous reading with simplified address counters
US6452864B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.