System and method for detecting double-bit errors and for correcting errors due to component failures
US6453440B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Aug 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a pair of global error correction codes, referred to generally as an untwisted global error correction code and a twisted global error correction code. Data at corresponding bit positions within the logical groups are conveyed through a common component. The untwisted global error correction code may be equivalent to the result of generating an individual error correction code for each logical group and XORing the collection of individual error correction codes together. The twisted global error correction code may be equivalent to the result of (or may be derived by) shifting (either linearly or cyclically) the error correction code for a given ith group by i bit positions, wherein i=0 to X−1, and by XORing corresponding columns of the resulting shifted error correction codes together. An error correction unit is coupled …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.