Timing diagram compiler and runtime environment for interactive generation of executable test programs for logic verification
US6453450B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A designer's timing diagram editor tool set provides programs for logic verification at logic design level. External stimulus to the design is done by a set of irritator programs created by the designer and derived from timing diagrams describing the input signals to be driven and/or the output signals to be checked of the logic under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format. Timing diagrams are then compiled into stand-alone executable programs. Sets of one or more executable timing diagrams (called buckets) can be defined. A simulation driver reads in the bucket file specified and randomly selects timing diagrams to stimulate the design under test with legal scenarios described in the timing diagrams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.