High and low voltage transistor manufacturing method
US6455386B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
The present invention relates to a method of manufacturing integrated circuits including high and low voltage MOS transistors. This method includes steps of forming insulated gate structure forming lightly-doped drain/source regions, depositing an insulating layer; forming a mask above the gates of the high voltage transistors which extends laterally beyond said gates; etching the insulating layer to leave spacers on the edges of the low voltage transistor gates; implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and forming in a self-aligned way a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.